1. Field of the Invention
Generally, the subject matter disclosed herein relates to integrated circuits, and, more particularly, to high performance transistors having recessed drain and source regions and strained channel regions by using stress sources, such as stressed overlayers, a strained semi-conductor alloy in drain and source areas to enhance charge carrier mobility in the channel region of a MOS transistor.
2. Description of the Related Art
Generally, a plurality of process technologies are currently practiced in the field of semiconductor production, wherein, for complex circuitry, such as microprocessors, advanced storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A MOS transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions with an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed near the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends, among other things, on the dopant concentration, the mobility of the majority charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as channel length. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the overall conductivity of the channel region substantially determines the performance of MOS transistors. Thus, the reduction of the channel length is a dominant design criterion for accomplishing an increase in the operating speed and packing density of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. One major problem in this respect is to provide low sheet and contact resistivity in drain and source regions and any contacts connected thereto and to maintain channel controllability. For example, reducing the channel length may necessitate an increase of the capacitive coupling between the gate electrode and the channel region, which may call for reduced thickness of the gate insulation layer. Presently, the thickness of silicon dioxide based gate insulation layers is in the range of 1-2 nm, wherein a further reduction may be less desirable in view of leakage currents, which typically exponentially increase when reducing the gate dielectric thickness. For this reason, in advanced transistor designs, a high-k dielectric material may be used in the gate dielectric layer, possibly in combination with a metal in the gate electrode, to enhance channel controllability and reduce signal propagation delay caused by a high gate resistivity of conventional gate materials, such as polysilicon in combination with a metal silicide.
The continuous size reduction of the critical dimensions, i.e., the gate length of the transistors, necessitates the adaptation and possibly the new development of highly complex process techniques concerning the above-identified problems. It has, therefore, been proposed to improve transistor performance by enhancing the channel conductivity of the transistor elements by increasing the charge carrier mobility in the channel region for a given channel length, thereby offering the potential for achieving a performance improvement that is comparable with the advance to a future technology node, while avoiding or at least postponing many of the above-mentioned problems, or achieving further increased performance when combined with other performance enhancing techniques, such as high-k gate dielectrics and the like. One efficient mechanism for increasing the charge carrier mobility is the modification of the lattice structure in the channel region, for instance by creating tensile or compressive stress in the vicinity of the channel region to produce a corresponding strain in the channel region, which results in a modified mobility for electrons and holes, respectively. For example, for standard silicon substrates, creating tensile strain in the channel region increases the mobility of electrons, which in turn may directly translate into a corresponding increase in the conductivity and thus drive current and operating speed. On the other hand, compressive strain in the channel region may increase the mobility of holes, thereby providing the potential for enhancing the performance of P-type transistors. The introduction of stress or strain engineering into integrated circuit fabrication is an extremely promising approach, since, for example, strained silicon may be considered as a “new” type of semiconductor material, which may enable the fabrication of fast powerful semiconductor devices without requiring expensive semiconductor materials, while many of the well-established manufacturing techniques may still be used.
According to one promising approach for creating strain in the channel region of transistor elements, the dielectric material that is formed above the basic transistor structure may be provided in a highly stressed state so as to induce a desired type of strain at the transistor and in particular in the channel region thereof. For example, the transistor structures are typically embedded in an interlayer dielectric material, which may provide the desired mechanical and electrical integrity of the individual transistor structures and which may provide a platform for the formation of additional wiring layers, which are typically required for providing the electrical interconnections between the individual circuit elements. That is, a plurality of wiring levels or metallization layers may typically be provided which may include horizontal metal lines and vertical vias including appropriate conductive materials for establishing the electrical connections. Consequently, an appropriate contact structure has to be provided which connects the actual circuit elements, such as transistors, capacitors and the like, or respective portions thereof, with the very first metallization layer. For this purpose, the interlayer dielectric material has to be appropriately patterned in order to provide respective openings connecting to the desired contact areas of the circuit elements, which may typically be accomplished by using an etch stop material in combination with the actual interlayer dielectric material.
For example, silicon dioxide is a well-established interlayer dielectric material in combination with silicon nitride, which may act as an efficient etch stop material during the formation of the contact openings. Consequently, the etch stop material, i.e., the silicon nitride material, is in close contact with the basic transistor structure and thus may be efficiently used for inducing strain in the transistors, in particular as silicon nitride may be deposited on the basis of well-established plasma enhanced chemical vapor deposition (PECVD) techniques with high internal stress. For instance, silicon nitride may be deposited with high internal compressive stress of up to 2 GPa and even higher by selecting appropriate deposition parameters. On the other hand, a moderately high internal tensile stress level may be created up to 1 GPa and higher by appropriately adjusting the process parameters, for instance, in particular the degree of ion bombardment during the deposition of the silicon nitride material. Consequently, the magnitude of the strain created in the channel region of a transistor element may depend on the internal stress level of the dielectric etch stop material and the thickness of stressed dielectric material in combination with the effective offset of the highly stressed dielectric material with respect to the channel region. Consequently, in view of enhancing transistor performance, it may be desirable to increase the internal stress level and also provide increased amounts of highly stressed dielectric material in the vicinity of the transistor element, while also positioning the stressed dielectric material as closely as possible to the channel region.
It turns out, however, that the internal stress levels of silicon nitride material may be restricted by the overall deposition capabilities of presently available PECVD techniques, while the effective layer thickness may also be substantially determined by the basic transistor topography and the distance between neighboring circuit elements. Consequently, although providing significant advantages, the efficiency of the stress transfer mechanism may depend significantly on process and device specifics and may result in reduced performance gain for well-established standard transistor designs having gate lengths of 50 nm and less, since the given device topography and the gap fill capabilities of the respective deposition process, in combination with a moderately high offset of the highly stressed material from the channel region caused by sophisticated spacer structures, may reduce the finally obtained strain in the channel region.
For these reasons, it has been suggested to use a recessed transistor architecture, i.e., an architecture in which portions of drain and source regions are recessed with respect to the channel region in the vicinity of the interface between the channel and the gate insulation layer in order to allow the deposition of the highly stressed dielectric material at a height level that corresponds to the channel region, thereby efficiently enhancing the lateral stress transfer mechanism into the channel region. This mechanism may be completed, for example, in some approaches with respect to enhancing performance of P-channel transistors, by providing a semiconductor material at least in portions of the drain and source areas in such a manner that a desired type of strain may be generated in the adjacent channel region. For this purpose, frequently, a silicon/germanium mixture or alloy may be used which may be epitaxially grown on a silicon template material, thereby creating a strained state of the silicon/germanium alloy, which may exert a certain stress on the adjacent channel region, thereby creating the desired type of strain therein. The magnitude of the strain in the channel region may be adjusted on the basis of the size of respective cavities in which the silicon/germanium alloy may be grown and by the amount of the germanium concentration in the semiconductor alloy. Since the respective strained semiconductor alloy may be positioned immediately adjacent to the channel region, a highly efficient strain-inducing mechanism may be provided. However, this strain-inducing mechanism may be difficult to be integrated into a process flow for providing a recessed transistor configuration, when the semiconductor alloy is provided in an early state of the process flow. That is, the process steps required for recessing the drain and source regions may affect other transistor components, such as the gate electrodes, the metal silicide regions that are typically to be formed on the drain and source regions and the like. Furthermore, the incorporation of sophisticated gate structures on the basis of high-k dielectrics and metal-containing electrode materials may also contribute to increased process complexity in combination with a recessed transistor configuration. However, in principle, each of these mechanisms may contribute to enhanced device performance.
The present disclosure is directed to various methods and devices that may avoid, or at least reduce, the effects of one or more of the problems identified above.